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ISL6257
Data Sheet January 17, 2007 FN9288.2
Highly Integrated Narrow VDC Battery Charger for Notebook Computers
The ISL6257 is a highly integrated battery charger controller for Li-Ion/Li-Ion polymer batteries. ISL6257 is designed for Narrow VDC applications where the system power source is either the battery pack or the regulated output of the charger. This makes the max voltage to the system equal to the max battery voltage instead of the max adapter voltage. Operating at lower system voltage can improve overall efficiency. High efficiency is achieved in the charger with a synchronous buck topology. The low-side MOSFET emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting. The constant output voltage can be selected for 2, 3 and 4 series Li-Ion cells with 0.5% accuracy over temperature. It can also be programmed between 4.2V + 5% per cell and 4.2V - 5% per cell to optimize battery capacity. When supplying the load and battery charger simultaneously, the input current limit for the AC adapter is programmable to within 3% accuracy to avoid overloading the AC adapter and to allow the system to make efficient use of available adapter power for charging. It also has a wide range of programmable charging current. The ISL6257 automatically transitions from regulating current mode to regulating voltage mode.
Features
* * * * * * * * * * * * * * * * * * * * 0.5% Charge Voltage Accuracy (-10C to +100C) 3% Accurate Input Current Limit 3% Accurate Battery Charge Current Limit 25% Accurate Battery Trickle Charge Current Limit Programmable Charge Current Limit, Adapter Current Limit and Charge Voltage Fixed 300kHz PWM Synchronous Buck Controller with Diode Emulation at Light Load AC Adapter Present Indicator Fast Input Current Limit Response Input Voltage Range 7V to 25V Support 2, 3 and 4 Cells Battery Pack Up to 17.64V Battery-Voltage Set Point Control Adapter Power Source Select MOSFET Thermal Shutdown Aircraft Power Capable DC Adapter Present Indicator Battery Discharge MOSFET Control Less than 10A Battery Leakage Current Support Pulse Charging Charge any Battery Chemistry: Li-Ion, NiCd, NiMH, etc. Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER (Notes 1, 2) ISL6257HRZ PART TEMP MARKING RANGE (C) PACKAGE (Pb-free) PKG. DWG. #
Applications
* Notebook, Desknote and Sub-notebook Computers * Personal Digital Assistant
ISL6257HRZ -10 to +100 28 Ld 5x5 QFN L28.5x5
Pinout
ISL6257 (28 LD QFN) TOP VIEW
DCPRN ACPRN 23 DCSET ACSET CSON 22 21 20 19 18 17 16 15 8 ACLIM 9 VADJ 10 GND 11 PGND 12 LGATE 13 VDDP 14 BOOT CSOP CSIN CSIP SGATE BGATE PHASE UGATE DCIN 25 VDD 26
ISL6257HRZ-T ISL6257HRZ -10 to +100 28 Ld 5x5 QFN L28.5x5 Tape & Reel NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
28 EN CELLS ICOMP VCOMP FB VREF CHLIM 1 2 3 4 5 6 7
27
24
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6257
Absolute Maximum Ratings
DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +28V CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V ACLIM, ACPRN, CHLIM, DCPRN, VDD to GND. . . . . . . -0.3V to 7V BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V ACSET and DCSET to GND (Note 1) . . . . . . . -0.3V to VDD + 0.3V FB, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD + 0.3V VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP + 0.3V PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) QFN Package (Notes 2, 3). . . . . . . . . . 39 9.5 QSOP Package (Note 2) . . . . . . . . . . . 80 NA Junction Temperature Range. . . . . . . . . . . . . . . . . .-10C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. ACSET and DCSET may be operated 1V below GND if the current through ACSET and DCSET is limited to less than 1mA. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT - PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F, IVDD = 0mA, TA = -10C to +100C, TJ +125C, unless otherwise noted. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY AND BIAS REGULATOR DCIN Input Voltage Range DCIN Quiescent Current Battery Leakage Current (Note 4) VDD Output Voltage/Regulation VDD Undervoltage Lockout Trip Point
7 EN = VDD or GND, 7V DCIN 25V DCIN = 0, no load 7V DCIN 25V, 0 IVDD 30mA VDD Rising Hysteresis 4.925 4.0 150 2.365 2.065 CSON = 16.8V, CELLS = VDD, VADJ = Float CSON = 12.6V, CELLS = GND, VADJ = Float CSON = 8.4V, CELLS = Float, VADJ = Float CSON = 17.64V, CELLS = VDD, VADJ = VREF CSON = 13.23V, CELLS = GND, VADJ = VREF CSON = 8.82V, CELLS = Float, VADJ = VREF CSON = 15.96V, CELLS = VDD, VADJ = GND CSON = 11.97V, CELLS = GND, VADJ = GND CSON = 7.98V, CELLS = Float, VADJ = GND -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 1.4 3 5.075 4.4 250 2.39 2.1
25 3 10 5.225 4.6 400 2.415 2.12 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
V mA A V V mV V V % % % % % % % % %
Reference Output Voltage VREF FB Feedback Voltage Battery Charge Voltage Accuracy
0 IVREF 300A
TRIP POINTS ACSET Threshold ACSET Input Bias Current Hysteresis ACSET Input Bias Current ACSET 1.26V 1.24 2.2 2.2 1.26 3.4 3.4 1.28 4.4 4.4 V A A
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FN9288.2 January 17, 2007
ISL6257
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT - PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F, IVDD = 0mA, TA = -10C to +100C, TJ +125C, unless otherwise noted. (Continued) TEST CONDITIONS ACSET < 1.26V MIN -1 1.24 2.2 DCSET 1.26V DCSET < 1.26V 2.2 -1 TYP 0 1.26 3.4 3.4 0 MAX 1 1.28 4.4 4.4 1 UNITS A V A A A
PARAMETER ACSET Input Bias Current DCSET Threshold DCSET Input Bias Current Hysteresis DCSET Input Bias Current DCSET Input Bias Current OSCILLATOR Frequency PWM Ramp Voltage (peak-peak) CSIP = 18V CSIP = 11V SYNCHRONOUS BUCK REGULATOR Maximum Duty Cycle UGATE Pull-Up Resistance UGATE Source Current UGATE Pull-Down Resistance UGATE Sink Current LGATE Pull-Up Resistance LGATE Source Current LGATE Pull-Down Resistance LGATE Sink Current Dead Time
245
300 1.6 1
355
kHz V V
97 BOOT - PHASE = 5V, 500mA source current BOOT - PHASE = 5V, BOOT-UGATE = 2.5V BOOT - PHASE = 5V, 500mA sink current BOOT - PHASE = 5V, UGATE - PHASE = 2.5V VDDP - PGND = 5V, 500mA source current VDDP - PGND = 5V, VDDP - LGATE = 2.5V VDDP - PGND = 5V, 500mA sink current VDDP - PGND = 5V, LGATE = 2.5V Falling UGATE to rising LGATE or falling LGATE to rising UGATE 10
99 1.8 1.0 1.0 1.8 1.8 1.0 1.0 1.8
99.6 3.0
% A
1.8
A
3.0
A
1.8
A
30
ns
CHARGING CURRENT SENSING AMPLIFIER Input Common-Mode Range Input Offset Voltage Input Bias Current at CSOP Input Bias Current at CSON CHLIM Input Voltage Range CSOP to CSON Full-Scale Current Sense Voltage CHLIM = 3.3V (4V3
FN9288.2 January 17, 2007
ISL6257
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT - PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F, IVDD = 0mA, TA = -10C to +100C, TJ +125C, unless otherwise noted. (Continued) TEST CONDITIONS 0 < CSIN < DCIN, Guaranteed by design MIN TYP 0.10 MAX 1 UNITS A
PARAMETER Input Bias Current at CSIN ADAPTER CURRENT LIMIT THRESHOLD CSIP to CSIN Full-Scale Current Sense Voltage
ACLIM = VREF ACLIM = Float ACLIM = GND
97 72 47 10 -20
100 75 50 16 -16
103 78 53 20 -10
mV mV mV A A
ACLIM Input Bias Current
ACLIM = VREF ACLIM = GND
VOLTAGE REGULATION ERROR AMPLIFIER Error Amplifier Transconductance from VFB to VCOMP CURRENT REGULATION ERROR AMPLIFIER Charging Current Error Amplifier Transconductance Adapter Current Error Amplifier Transconductance BATTERY CELL SELECTOR CELLS Input Voltage for 4 Cell Select CELLS Input Voltage for 3 Cell Select CELLS Input Voltage for 2 Cell Select MOSFET DRIVER BGATE Pull-Up Current BGATE Pull-Down Current CSIP - BGATE Voltage High CSIP - BGATE Voltage Low DCIN - CSON Threshold for CSIP-BGATE Going High DCIN - CSON Threshold Hysteresis SGATE Pull-Up Current SGATE Pull-Down Current CSIP - SGATE Voltage High CSIP - SGATE Voltage Low CSIP - CSIN Threshold for CSIP - SGATE Going High CSIP - CSIN Threshold Hysteresis LOGIC INTERFACE EN Input Voltage Range EN Threshold Voltage Rising Falling Hysteresis EN Input Bias Current ACPRN Sink Current ACPRN Leakage Current EN = 2.5V ACPRN = 0.4V ACPRN = 5V 0 1.030 0.985 30 1.8 3 -0.5 1.06 1.000 60 2.0 8 VDD 1.100 1.025 90 2.2 11 0.5 V V V mV A mA A CSIP - SGATE = 3V CSIP - SGATE = 5V DCIN = 12V, CSON Rising CSIP - BGATE = 3V CSIP - BGATE = 5V 10 2.7 8 -50 -100 250 7 50 8 -50 2.5 1.3 30 4.0 9.6 0 0 300 12 160 9 0 8 5 45 5.0 11 50 100 400 15 370 11 50 13 8 mA mA V mV mV mV mA A V mV mV mV 2.1 4.3 2 4.2 V V V from VCA2 to ICOMP from VCA1 to ICOMP 50 50 A/V A/V 240 A/V
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FN9288.2 January 17, 2007
ISL6257
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT - PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F, IVDD = 0mA, TA = -10C to +100C, TJ +125C, unless otherwise noted. (Continued) TEST CONDITIONS DCPRN = 0.4V DCPRN = 5V CSON = 12.6V MIN 3 -0.5 315 380 150 25 TYP 8 MAX 11 0.5 485 UNITS mA A k C C
PARAMETER DCPRN Sink Current DCPRN Leakage Current CSON to GND resistance Thermal Shutdown Temperature Thermal Shutdown Temperature Hysteresis NOTE:
4. This is the sum of currents in these pins (CSIP, CSIN, BGATE, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM.
Typical Operating Performance
0.6 VDD LOAD REGULATION ACCURACY(%)
DCIN = 20V, 4S2P Li-Battery, TA = +25C, unless otherwise noted.
0.10 VREF LOAD REGULATION ACCURACY(%)
0.08
0.3
0.06
0.0
0.04
-0.3
0.02
-0.6
0
5
10
15
20
40
0.00
0
100
200 LOAD CURRENT (A)
300
400
LOAD CURRENT (mA)
FIGURE 1. VDD LOAD REGULATION
FIGURE 2. VREF LOAD REGULATION
100
10 9 EFFICIENCY (%) 8 | ACCURACY | (%) 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100
96
92 VCSON = 8.4V 2 CELLS 88 VCSON = 12.6V 3 CELLS 84 VCSON = 16.8V 4 CELLS
80
76
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CSIP-CSIN (mV)
LOAD CURRENT (A)
FIGURE 3. ACCURACY vs AC ADAPTER CURRENT
FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT
5
FN9288.2 January 17, 2007
ISL6257 Typical Operating Performance
DCIN = 20V, 4S2P Li-Battery, TA = +25C, unless otherwise noted. (Continued)
LOAD CURRENT 5A/div ADAPTER CURRENT 5A/div CHARGE CURRENT 2A/div LOAD STEP: 0-4A CHARGE CURRENT: 3A AC ADAPTER CURRENT LIMIT: 5.15A
DCIN 10V/div
ACSET 1V/div
DCSET 1V/div
DCPRN 5V/div ACPRN 5V/div
BATTERY VOLTAGE 2V/div
FIGURE 5. AC AND DC ADAPTER DETECTION
FIGURE 6. LOAD TRANSIENT RESPONSE
CSON 5V/div EN 5V/div
INDUCTOR CURRENT 2A/div
BATTERY INSERTION BATTERY REMOVAL
CSON 10V/div
INDUCTOR CURRENT 2A/div
VCOMP
CHARGE CURRENT 2A/div
VCOMP 2V/div ICOMP 2V/div
ICOMP
FIGURE 7. CHARGE ENABLE AND SHUTDOWN
FIGURE 8. BATTERY INSERTION AND REMOVAL
CHLIM=0.2V CSON=8V
PHASE 10V/div
PHASE 10V/div
INDUCTOR CURRENT 1A/div
UGATE 2V/div
UGATE 5V/div
LGATE 2V/div
FIGURE 9. SWITCHING WAVE FORMS IN DISCONTINUOUS CONDUCTION MODE (DIODE EMULATION)
FIGURE 10. SWITCHING WAVE FORMS IN CONTINUOUS CONDUCTION MODE
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FN9288.2 January 17, 2007
ISL6257 Typical Operating Performance
DCIN = 20V, 4S2P Li-Battery, TA = +25C, unless otherwise noted. (Continued)
ADAPTER REMOVAL
SGATE-CSIP 2V/div
BGATE-CSIP 2V/div
SYSTEM BUS VOLTAGE 10V/div BGATE-CSIP 2V/div INDUCTOR CURRENT 2A/div
ADAPTER INSERTION
SYSTEM BUS VOLTAGE 10V/div
SGATE-CSIP 2V/div INDUCTOR CURRENT 2A/div
FIGURE 11. ADAPTER REMOVAL
FIGURE 12. ADAPTER INSERTION
FIGURE 13. ADAPTER INSERTION WITH A CHARGED BATTERY
FIGURE 14. ADAPTER INSERTION WITH NO BATTERY AND A 2A SYSTEM LOAD
ISL6257 CHARGE CURVES
13 2.5
100%
Efficiency vs load current
95%
2.0
BATTERY VOLTAGE
11
Efficiency
V battery I battery
1.5
BATTERY CURRENT
12
90% 85% 80% 75%
10Vin-8.4Vout 25Vin-8.4Vout 15Vin-12.6Vout 25Vin-12.6Vout 20Vin-16.8Vout 25Vin-16.8Vout
1.0 10 0.5
9 0 50 100
TIME (MINUTES)
150
0.0 200
70% 0 2 4 6 8 10 12
Load Current (Amps)
FIGURE 15. BATTERY CHARGE VOLTAGE AND CURRENT
FIGURE 16. EFFICIENCY VS LOAD CURRENT
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FN9288.2 January 17, 2007
ISL6257 Typical Operating Performance
18 16 14 12
10Vin-8.4Vout 15Vin-8.4Vout 20Vin-8.4Vout 25Vin-8.4Vout 15Vin-12.6Vout 20Vin-12.6Vout 25Vin-12.6Vout 20Vin-16.8Vout 25Vin-16.8Vout
DCIN = 20V, 4S2P Li-Battery, TA = +25C, unless otherwise noted. (Continued)
0.6%
Line and Load Regulation
Vout relative to Vout at 0 Load
0.4%
Line and Load Regulation (%)
10Vin-8.4Vout 15Vin-8.4Vout 20Vin-8.4Vout 25Vin-8.4Vout 15Vin-12.6Vout 20Vin-12.6Vout 25Vin-12.6Vout 20Vin-16.8Vout 25Vin-16.8Vout upper limit lowerlimit
0.2%
Vout (V)
10 8 6 4 2 0 0 2 4 6 8 10 12 System Load Current (Amps)
0.0%
-0.2%
Adapter Current Limit Mode
-0.4%
Adapter Current Limit Mode
-0.6% 0 2 4 6 8 10 12 System Load Current (Amps)
FIGURE 17. LINE AND LOAD REGULATION IN NVDC MODE
FIGURE 18. LINE AND LOAD REGULATION IN NVDC MODE AS A PERCENTAGE OF NO LOAD VOLTAGE
Functional Pin Descriptions
BOOT
Connect BOOT to a 0.1F ceramic capacitor to PHASE pin and connect to the cathode of the bootstrap Schottky diode.
CSIP/CSIN
CSIP/CSIN is the AC adapter current sensing positive/negative input. The differential voltage across CSIP and CSIN is used to sense the AC adapter current, and is compared with the AC adapter current limit to regulate the AC adapter current.
UGATE
UGATE is the high-side MOSFET gate drive output.
GND
GND is an analog ground.
SGATE
SGATE is the AC adapter power source select output. The SGATE pin drives an external P-MOSFET used to switch to AC adapter as the system power source.
DCIN
The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect a 0.1F ceramic capacitor from DCIN to CSON.
BGATE
Battery power source select output. This pin drives an external P-channel MOSFET used to switch the battery as the system power source in non Narrow VDC systems. When the voltage at CSON pin is higher than the AC adapter output voltage at DCIN, BGATE is driven to low and selects the battery as the power source. In Narrow VDC systems BGATE should be unconnected.
ACSET
ACSET is an AC adapter detection input. Connect to a resistor divider from the AC adapter output.
ACPRN
Open-drain output signals AC adapter is present. ACPRN pulls low when ACSET is higher than 1.26V and pulled high when ACSET is lower than 1.26V.
LGATE
LGATE is the low-side MOSFET gate drive output; swing between 0V and VDDP.
DCSET
DCSET is a lower voltage adapter detection input (like aircraft power 15V). Allows the adapter to power the system where battery charging has been disabled.
PHASE
The Phase connection pin connects to the high-side MOSFET source, output inductor, and low-side MOSFET drain.
DCPRN
Open-drain output signals DC adapter is present. DCPRN pulls low when DCSET is higher than 1.26V and pulled high when DCSET is lower than 1.26V.
CSOP/CSON
CSOP/CSON is the battery charging current sensing positive/negative input. The differential voltage across CSOP and CSON is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. The CSON pin is also used as the battery feedback voltage to perform voltage regulation.
EN
EN is the Charge Enable input. Connecting EN to high enables the charge control function; connecting EN to low disables charging functions. Use with a thermistor to detect a hot battery and suspend charging.
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FN9288.2 January 17, 2007
ISL6257
FB
The negative feedback of the voltage amplifier which sets the output voltage at CSON. An internal resistor divider from CSON adjusts the voltage feedback signal in the ratio of 6:1 for CELLS = GND, 8:1 for CELLS = VDD and 4:1 for CELLS = float.
CELLS
This pin is used to select the battery voltage. CELLS = VDD for a 4S battery pack, CELLS = GND for a 3S battery pack, CELLS = Float for a 2S battery pack.
VADJ
VADJ adjusts battery regulation voltage. VADJ = VREF for 4.2V + 5% per cell; VADJ = Floating for 4.2V per cell; VADJ = GND for 4.2V - 5% per cell. Connect to a resistor divider to program the desired battery cell voltage between 4.2V - 5% and 4.2V + 5%.
PGND
PGND is the power ground. Connect PGND to the source of the low-side MOSFET.
VDD
VDD is an internal LDO output to supply IC analog circuit. Connect a 1F ceramic capacitor to ground.
CHLIM
CHLIM is the battery charge current limit set pin.CHLIM input voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set point for CSOP - CSON is 165mV. The charger shuts down if CHLIM is forced below 88mV.
VDDP
VDDP is the supply voltage for the low-side MOSFET gate driver. Connect a 4.7 resistor to VDD and a 1F ceramic capacitor to power ground.
ACLIM
ACLIM is the adapter current limit set pin. ACLIM = VREF for 100mV, ACLIM = Floating for 75mV, and ACLIM = GND for 50mV. Connect a resistor divider to program the adapter current limit threshold between 50mV and 100mV.
ICOMP
ICOMP is a current loop error amplifier output.
VCOMP
VCOMP is a voltage loop amplifier output.
VREF
VREF is a 2.39V reference output pin. It is internally compensated. Do not connect a decoupling capacitor.
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FN9288.2 January 17, 2007
ISL6257
SGATE
CSIP CSIN
DCSET
DCPRN
ACSET ACPRN
+X19.9CA1
+
1.26V
+
BGATE
VREF 152k ACLIM 152k
1.26V CSON
ADAPTER CURRENT LIMIT SET gm3
+
DCIN LDO REGULATOR VDD
+
ICOMP
MIN CURRENT BUFFER 300kHz RAMP MIN VOLTAGE BUFFER
BOOT
PWM
UGATE PHASE
+
VCOMP VREF 514k gm1 VDDP LGATE
+
VADJ 514k
-
288k 32k 16k 48k
-
gm2
PGND
+
2.1V
-
1.065V EN
CELLS
VOLTAGE SELECTOR VDD
-
CA2 X19.9
+
+
VREF
REFERENCE GND FB CSIP CSOP CHLIM
FIGURE 19. FUNCTIONAL BLOCK DIAGRAM
10
FN9288.2 January 17, 2007
ISL6257
ADAPTER
R8 100k 1% R9 11.5k 1%
R8 130k 1% R9 10.2k 1%
VDD
Q3
Q5 0.1F
CSON
DCIN ACSET DCSET
SGATE
CSIP
CF2 1F
CSIN
RS2 20m
VDDP
C7 1F
R20 4.7 C9
VDD
ISL6257
RF2 18
VDDP BOOT UGATE
HOST
VCC
D2 Q1 C24 0.1F
1F
C21 22F
R5 100k
DIGITAL INPUT DIGITAL INPUT
R16 100k
ACPRN DCPRN PGND EN PHASE LGATE
Q2
D1 OPTIONAL RF1
L 4.7H SYSTEM LOAD Co 330F
DIGITAL OUTPUT
CSON
CSOP ICOMP
R1 3K C1 470pF
CF1 1F
CSON
2.2
C6 33nF R2 56k C2 1nF
FB
RS1 10m
BAT+
VCOMP
Q6
BGATE
C10 10F
BAT-
A/D OUTPUT
ACLIM VREF CELLS
A/D OUTPUT FLOATING 4.2V/CELL
CHLIM VADJ GND
3S2P BATTERY PACK
BATTERY ISOLATION FET SCL SDA A/D INPUT GND SCL SDA TEMP
FIGURE 20. ISL6257 TYPICAL NVDC APPLICATION CIRCUIT WITH P CONTROL
11
FN9288.2 January 17, 2007
ISL6257 Theory of Operation
Introduction
The ISL6257 includes all of the functions necessary to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A. The ISL6257 has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current. VADJ and CELLS inputs are used to control charge voltage. The ISL6257 charges the battery with constant charge current (set by the CHLIM input) until the battery voltage rises to a programmed charge voltage (set by the VADJ and CELLS input) then the charger begins to operate in a constant voltage mode. The charger also drives an adapter isolation P-channel MOSFET on SGATE to efficiently switch in the adapter supply. The EN input allows shutdown of the charger through a command from a micro-controller. It also uses EN to safely shutdown the charger when the battery is in extremely hot conditions. Figure 19 shows the IC functional block diagram. The synchronous buck converter uses external N-channel MOSFETs to convert the input voltage to the required charging current and charging voltage. Figure 20 shows the ISL6257 typical application circuit which uses a micro-controller to adjust the charging current set by CHLIM input for aircraft power applications. The voltage at CHLIM and the value of R11 sets the charging current. The DC/DC converter generates the control signals to drive two external N-channel MOSFETs to regulate the voltage and current set by the ACLIM, CHLIM, VADJ and CELLS inputs. The ISL6257 features a voltage regulation loop (VCOMP) and two current regulation loops (ICOMP). The VCOMP voltage regulation loop monitors CSON to ensure that its voltage never exceeds the battery charge voltage set by VADJ and CELLS. The ICOMP current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by CHLIM; and the ICOMP current regulation loops also regulate the input current drawn from the AC adapter to ensure that it never exceeds the input current limit set by ACLIM, and to prevent a system crash and AC adapter overload. An adaptive gate drive scheme is used to control the dead time between two switches. The dead time control circuit monitors the LGATE output and prevents the upper side MOSFET from turning on until LGATE is fully off, preventing cross-conduction and shoot-through. In order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the LGATE driver to MOSFET gate, and from the source of MOSFET to PGND. The external Schottky diode is between the VDDP pin and BOOT pin to keep the bootstrap capacitor charged.
Setting the Battery Regulation Voltage
The ISL6257 uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. The VADJ input adjusts the charger output voltage. The VADJ control voltage can vary from 0 to VREF, providing a 10% adjustment range (from 4.2V - 5% per cell to 4.2V + 5% per cell) on CSON regulation voltage. An overall voltage accuracy of better than 0.5% is achieved. The per-cell battery termination voltage is a function of the battery chemistry. Consult the battery manufacturers to determine this voltage. * Float VADJ to set the battery voltage VCSON = 4.2V x number of the cells, * Connect VADJ to VREF to set 4.41V x number of cells, * Connect VADJ to ground to set 3.99V x number of the cells. So, the maximum battery voltage of 17.6V can be achieved. Note that other battery charge voltages can be set by connecting a resistor divider from VREF to ground. The resistor divider should be sized to draw no more than 100A from VREF or connect a low impedance voltage source like the D/A converter in the micro-controller. The programmed battery voltage per cell can be determined by Equation 1:
V CELL = 0.175 V VADJ + 3.99V (EQ. 1)
An external resistor divider from VREF sets the voltage at VADJ according to Equation 2:
R bot_VADJ || 514k V VADJ = VREF x -------------------------------------------------------------------------------------------------------R top_VADJ || 514k + R bot_VADJ || 514k (EQ. 2)
PWM Control
The ISL6257 employs a fixed frequency PWM voltage mode control architecture with a feed-forward function. The feed-forward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. When the battery charge voltage approaches the input voltage, the DC/DC converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. It can achieve duty cycle of up to 99.6%.
To minimize accuracy loss due to interaction with VADJ's internal resistor divider, ensure the AC resistance looking back into the external resistor divider is less than 25k. Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. The internal error amplifier gm1 maintains voltage regulation. The voltage error amplifier is compensated at VCOMP. The component values shown in Figure 20 provide suitable performance for most applications. Individual compensation of the voltage
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ISL6257
regulation and current-regulation loops allows for optimal compensation.
TABLE 1. CELL NUMBER PROGRAMMING CELLS VDD GND Float CELL NUMBER 4 3 2
the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using the input current limiter, the current capability of the AC adapter can be lowered, reducing system cost. The ISL6257 limits the battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter voltage. This constant input current regulation allows the adapter to fully power the system and prevent the AC adapter from overloading and crashing the system bus. An internal amplifier gm3 compares the voltage between CSIP and CSIN to the input current limit threshold voltage set by ACLIM. Connect ACLIM to REF, Float and GND for the full-scale input current limit threshold voltage of 100mV, 75mV and 50mV, respectively, or use a resistor divider from VREF to ground to set the input current limit as Equation 5:
0.05 1 I INPUT = ----- --------------- V ACLIM + 0.05 R 2 VREF R bot, ACLIM || 152k V ACLIM = VREF ----------------------------------------------------------------------------------------------------------------- R top, ACLIM || 152k + R bot, ACLIM || 152k (EQ. 5)
Setting the Battery Charge Current Limit
The CHLIM input sets the maximum charging current. The current set by the current sense-resistor connects between CSOP and CSON. The full-scale differential voltage between CSOP and CSON is 165mV for CHLIM = 3.3V, so the maximum charging current is 4.125A for a 40m sensing resistor. Other battery charge current-sense threshold values can be set by connecting a resistor divider from VREF or 3.3V to ground, or by connecting a low impedance voltage source like a D/A converter in the micro-controller. Unlike VADJ and ACLIM, CHLIM does not have an internal resistor divider network. The charge current limit threshold is given by Equation 3:
165mV V CHLIM I CHG = ----------------- --------------------- R 3.3V
1
(EQ. 3)
To set the trickle charge current for the dumb charger, an A/D output controlled by the micro-controller is connected to CHLIM pin. The trickle charge current is determined by Equation 4:
165mV V CHLIM ,trickle I CHG = ----------------- -------------------------------------- R 3.3V
1
(EQ. 4)
When the CHLIM voltage is below 88mV (typical), it will disable the battery charge. When choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing efficiency. However, adjusting CHLIM voltage to reduce the voltage across the current sense resistor R11 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. There is a trade-off between accuracy and power dissipation. A low pass filter is recommended to eliminate switching noise. Connect the resistor to the CSOP pin instead of the CSON pin, as the CSOP pin has lower bias current and less influence on current-sense accuracy and voltage regulation accuracy.
When choosing the current sense resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficiency. The AC adapter current sense accuracy is very important. Use a 1% tolerance current-sense resistor. The highest accuracy of 1.5% is achieved with 100mV current-sense threshold voltage for ACLIM = VREF, but it has the highest power dissipation. For example, it has 400mW power dissipation for rated 4A AC adapter and 1W sensing resistor may have to be used. 2.5% and 4.5% accuracy can be achieved with 75mV and 50mV current-sense threshold voltage for ACLIM = Floating and ACLIM = GND, respectively. A low pass filter is suggested to eliminate the switching noise. Connect the resistor to CSIN pin instead of CSIP pin because CSIN pin has lower bias current and less influence on the current-sense accuracy.
Setting the Input Current Limit
The total input current from an AC adapter, or other DC source, is a function of the system supply current and the battery-charging current. The input current regulator limits the input current by reducing the charging current, when the input current exceeds the input current limit set by ACLIM. System current normally fluctuates as portions of the system are powered up or down. Without input current regulation,
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AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to ACSET to detect when AC power is available, as shown in Figure 20. ACPRN is an open-drain output and is high when ACSET is less than Vth,fall, and active low when ACSET is above Vth,rise. Vth,rise and Vth,fall are given by Equation 6 and Equation 7:
R8 V th, rise = ----- + 1 V ACSET R9 R8 V th, fall = ----- + 1 V ACSET - I hys R 8 R9 (EQ. 6)
(EQ. 7)
EN can be driven by a thermistor to allow automatic shutdown of the ISL6257 when the battery pack is hot. Often an NTC thermistor is included inside the battery pack to measure its temperature. When connected to the charger, the thermistor forms a voltage divider with a resistive pull-up to the VREF. The threshold voltage of EN is 1.0V with 60mV hysteresis. The thermistor can be selected to have a resistance vs temperature characteristic that abruptly decreases above a critical temperature. This arrangement automatically shuts down the ISL6257 when the battery pack is above a critical temperature. Another method for inhibiting charging is to force CHLIM below 85mV (typ).
where: * Ihys is the ACSET input bias current hysteresis, and * VACSET = 1.24V (min), 1.26V (typ) and 1.28V (max). The hysteresis is IhysR8, where Ihys = 2.2A (min), 3.4A (typ) and 4.4A (max).
Supply Isolation
If the voltage across the adapter sense resistor R2 is typically greater than 8mV, the P-channel MOSFET controlled by SGATE is turned on reducing the power dissipation. If the voltage across the adapter sense resistor R2 is less than 3mV, SGATE turns off the P-channel MOSFET isolating the adapter from the system bus.
DC Adapter Detection
Connect the DC input through a resistor divider to DCSET to detect when lower voltage (i.e. aircraft) DC power is available. DCPRN is an open-drain output and is high when DCSET is less than Vth,fall, and active low when DCSET is above Vth,rise. Vth,rise and Vth,fall are given by Equation 8 and Equation 9:
R 24 V th, rise = -------- + 1 * V DCSET R 25 R 24 V th, fall = -------- + 1 * V DCSET - I hys R 24 R 25 (EQ. 8)
Battery Power Source Selection and Aircraft Power Application
The battery voltage is monitored by CSON. If the battery voltage measured on CSON is less than the adapter voltage measured on DCIN, then the P-channel MOSFET controlled by SGATE is allowed to turn on when the adapter current is high enough. If it is greater, then the P-channel MOSFET controlled by SGATE turns off. When operating on aircraft power it is desirable to disable charging to minimize loading of the aircraft power systems. DCIN is usually lower when connected to aircraft power (15V) than it is when connected AC power (20V). The DCSET pin provides means of detecting this lower DC input voltage. If the DC input voltage is below the ACSET threshold and above the DCET threshold, ACPRN will be high and DCPRN will be low, and the host may turn off Q5 (Figure 20) to stop charging the battery.
(EQ. 9)
where: * Ihys is the DCSET input bias current hysteresis, and * VDCSET = 1.24V (min), 1.26V (typ) and 1.28V (max). The hysteresis is IhysR14, where Ihys = 2.2A (min), 3.4A (typ) and 4.4A (max).
LDO Regulator
VDD provides a 5.0V supply voltage from the internal LDO regulator from DCIN and can deliver up to 30mA of current. The MOSFET drivers are powered by VDDP, which must be connected to VDDP as shown in Figure 20. VDDP connects to VDD through an external low pass filter. Bypass VDDP and VDD with a 1F capacitor.
Short Circuit Protection
Since the battery charger will regulate the charge current to the limit set by CHLIM, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery.
Over Temperature Protection
If the die temperature exceeds +150C, it stops charging. Once the die temperature drops below +125C, charging will start up again.
Shutdown
The ISL6257 features a low-power shutdown mode. Driving EN low shuts down the ISL6257. In shutdown, the DC/DC converter is disabled, and VCOMP and ICOMP are pulled to ground. The ACPRN and DCPRN outputs continue to function.
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ISL6257 Application Information
The following battery charger design refers to the typical application circuit in Figure 20, where typical battery configuration of 3S2P is used. This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, and current sensing resistors. where the duty cycle D is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode, which is typical operation for the battery charger. During the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. So, the duty cycle change can be in the range of between 0.5 and 0.88 for the minimum battery voltage of 10V (2.5V/Cell) and the maximum battery voltage of 16.8V. The maximum RMS value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as Equation 14:
V IN, MAX I RMS = ---------------------------------------4 12 L F SW (EQ. 14)
Inductor Selection
The inductor selection has trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the size, but ripple current is higher. This also results in higher AC losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher DCR (DC resistance of the inductor) loss, and has slower transient response. So, the practical inductor design is based on the inductor ripple current being 15% to 20% of the maximum operating DC current at maximum input voltage. Maximum ripple is at 50% duty cycle or VBAT = VIN,MAX/2. The required inductance can be calculated from Equation 10:
R IN, MAX L = -----------------------------------------4 I SW I RIPPLE (EQ. 10)
For VIN,MAX = 19V, L = 4.7H, and fs = 300kHz, the maximum RMS current is 0.98A. Ceramic capacitors are good choices to absorb this current and also has very small size. Organic polymer capacitors have high capacitance with small size and have a significant equivalent series resistance (ESR). Although ESR adds to ripple voltage, it also creates a high frequency zero that helps the closed loop operation of the buck regulator. EMI considerations usually make it desirable to minimize ripple current in the battery leads. Beads may be added in series with the battery pack to increase the battery impedance at 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and battery impedance. If the ESR of the output capacitor is 10m and battery impedance is raised to 2 with a bead, then only 0.5% of the ripple current will flow in the battery. MOSFET Selection The notebook battery charger synchronous buck converter has the input voltage from the AC adapter output. The maximum AC adapter output voltage does not exceed 25V. Therefore, MOSFETs should be used that are rated for 30V VDS with low rDS(ON) at 5V VGS. The high-side MOSFET must be able to dissipate the conduction losses plus the switching losses. For the battery charger application, the input voltage of the synchronous buck converter is equal to the AC adapter output voltage, which is relatively constant. The maximum efficiency is achieved by selecting a high-side MOSFET that has the conduction losses equal to the switching losses. Switching losses in the low-side FET are very small. The choice of low-side FET is a trade off between conduction losses (rDS(ON)) and cost. A good rule of thumb for the rDS(ON) of the low-side FET is 2X the rDS(ON) of the high-side FET. The ISL6257 LGATE gate driver can drive sufficient gate current to switch most MOSFETs efficiently. However, some FETs may exhibit cross conduction (or shoot through) due to current injected into the drain-to-source parasitic capacitor (Cgd) by the high dV/dt rising edge at phase node when the high-side MOSFET turns on. Although LGATE sink current (1.8A typical) is more than enough to switch the FET off
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Where VIN,MAX and fSW are the maximum input voltage, and switching frequency, respectively. The inductor ripple current I is found from Equation 11:
I RIPPLE = 0.3 I L, MAX (EQ. 11)
where the maximum peak-to-peak ripple current is 30% of the maximum charge current is used. For VIN,MAX = 19V, VBAT = 12.6V, IL,MAX = 10A, and fs = 300kHz, the calculated inductance is 4.7H. Ferrite cores are often the best choice since they are optimized at 300kHz to 600kHz operation with low core loss. The core must be large enough not to saturate at the peak inductor current IPeak in Equation 12:
1 I PEAK = I L, MAX + -- I RIPPLE 2 (EQ. 12)
Output Capacitor Selection The output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and supply very high di/dt load transients. In a Narrow VDC system the output capacitance is also the bypass capacitance on the input of the CORE regulator and may be several hundred F. The following examples use 330F with ESR = 6m. The RMS value of the output ripple current Irms is given by Equation 13:
V IN, MAX I RMS = --------------------------------- D ( 1 - D ) 12 L F SW (EQ. 13)
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ISL6257
quickly, voltage drops across parasitic impedances between LGATE and the MOSFET can allow the gate to rise during the fast rising edge of voltage on the drain. MOSFETs with low threshold voltage (<1.5V) and low ratio of Cgs/Cgd (<5) and high gate resistance (>4) may be turned on for a few ns by the high dV/dt (rising edge) on their drain. This can be avoided with higher threshold voltage and Cgs/Cgd ratio. Another way to avoid cross conduction is slowing the turn-on speed of the high-side MOSFET by connecting a resistor between the BOOT pin and the boot strap cap. For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage as shown in Equation 15:
V OUT 2 P Q1, conduction = -------------- I BAT r DS ( ON ) V IN (EQ. 15)
For the low-side MOSFET, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage (Equation 17):
V OUT 2 P Q2 = 1 - -------------- I BAT r DS ( ON ) V IN (EQ. 17)
Choose a low-side MOSFET that has the lowest possible on-resistance with a moderate-sized package like the SO-8 and is reasonably priced. The switching losses are not an issue for the low-side MOSFET because it operates at zero-voltage-switching. Choose a Schottky diode in parallel with low-side MOSFET Q2 with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the low-side MOSFET Q2 body diode. As a general rule, select a diode with DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs should be less than 24mA. So, the total gate charge for the high-side and low-side MOSFETs is limited by Equation 18:
1 GATE Q GATE ---------------f sw (EQ. 18)
The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, pull-up and pull-down resistance of the gate driver. The following switching loss calculation (Equation 16) provides a rough estimate.
P Q1, Switching = Q gd 1 Q gd 1 -- V IN I LV f sw ---------------------- + -- V IN I LP f sw ---------------- + Q rr V IN f sw I g, source 2 2 I g, sin k (EQ. 16)
where the following are the peak gate-drive source/sink current of Q1, respectively: * Qgd: drain-to-gate charge, * Qrr: total reverse recovery charge of the body-diode in low-side MOSFET, * ILV: inductor valley current, * ILP: Inductor peak current, * Ig,sink * Ig,source To achieve low switching losses, it requires low drain-to-gate charge Qgd. Generally, the lower the drain-to-gate charge, the higher the on-resistance. Therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is a product of the total gate charge and on-resistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application.
where IGATE is the total gate drive current and should be less than 24mA. Substituting IGATE = 24mA and fs = 300kHz into Equation 18 yields that the total gate charge should be less than 80nC. Therefore, the ISL6257 easily drives the battery charge current up to 8A. Snubber Design ISL6257's buck regulator operates in discontinuous current mode (DCM) when the load current is less than half the peak-to-peak current in the inductor. After the low-side FET turns off, the phase voltage rings due to the high impedance with both FETs off. This can be seen in Figure 9. Adding a snubber (resistor in series with a capacitor) from the phase node to ground can greatly reduce the ringing. In some situations a snubber can improve output ripple and regulation. The snubber capacitor should be approximately twice the parasitic capacitance on the phase node. This can be estimated by operating at very low load current (100mA) and measuring the ringing frequency.
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CSNUB and RSNUB can be calculated from Equation 19:
2 C SNUB = --------------------------------2 ( 2f ring ) L 1 R SNUB = ----------------------------------------2 C SNUB f ring (EQ. 19) PARTS R24 R15 R16 TABLE 2. COMPONENT LIST (Continued) PART NUMBERS AND MANUFACTURER 100k, 1%, (0805) 11.5k, 1%, (0805) 100k, 1%, (0805)
Input Capacitor Selection The input capacitor absorbs the ripple current from the synchronous buck converter, which is given by Equation 20:
V OUT ( V IN - V OUT ) I RMS = I BAT ---------------------------------------------------------V
IN
(EQ. 20)
This RMS ripple current must be smaller than the rated RMS current in the capacitor datasheet. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents when the AC adapter is plugged into the battery charger. For notebook battery charger applications, it is recommend that ceramic capacitors or polymer capacitors from Sanyo be used due to their small size and reasonable cost. Table 2 shows the component lists for the typical application circuit in Figure 20.
TABLE 2. COMPONENT LIST PARTS C21, C10 C12, C24 C3, C7, C9 C2 C6 Co C1 D1 D2 L Q1 Q2 Q3 Q5 Q6 R1 R2 RS1 RS2 RF2 RF1 R5, R7 R8 R9 R20 PART NUMBERS AND MANUFACTURER 22F/25V ceramic capacitor, TDK, C5750X7R1E226M 0.1F/50V ceramic capacitor 1F/10V ceramic capacitor, Taiyo Yuden LMK212BJ105MG 1nF ceramic capacitor 33nF ceramic capacitor 330F, 6m electrolytic capacitor (system load) 470pF ceramic capacitor 30V/3A Schottky diode, EC31QS03L (optional) 100mA/30V Schottky Diode, Central Semiconductor 4.7H/10.2A/8.8m, Toko, FDA1254-4R7M 6m/30V, HAT2168HFDS6912A, Fairchild 2.5m/30V HAT2165H -30V/30m, Si4835BDY, Siliconix Signal P-channel MOSFET, NDS352AP -30V/30m, Si4835BDY, Siliconix 3k, 1%, (0805) 56k, 1%, (0805) 10m, 1%, LRC-LR2512-01-R010-F, IRC 20m, 1%, LRC-LR2010-01-R020-F, IRC 18, 5%, (0805) 2.2, 5%, (0805) 100k, 5%, (0805) 130k, 1%, (0805) 10.2k, 1%, (0805) 4.7, 5%, (0805)
Loop Compensation Design ISL6257 has three closed loop control modes. One controls the output voltage when the battery is fully charged or absent. A second controls the current into the battery when charging and the third limits current drawn from the adapter. The charge current and input current control loops are compensated by a single capacitor on the ICOMP pin. The voltage control loop is compensated by a network shown in Figure 23. Descriptions of these control loops and guidelines for selecting compensation components will be given in the following sections. Which loop controls the output is determined by the minimum current buffer and the minimum voltage buffer shown in Figure 19. These three loops will be described separately. Transconductance Amplifiers gm1, gm2 and gm3 ISL6257 uses several transconductance amplifiers (also known as gm amps). Most commercially available op amps are voltage controlled voltage sources with gain expressed as A = VOUT/VIN. gm amps are voltage controlled current sources with gain expressed as gm = IOUT/VIN. gm will appear in some of the equations for poles and zeros in the compensation. PWM Gain Fm The Pulse Width Modulator in the ISL6257 converts voltage at VCOMP (or ICOMP) to a duty cycle by comparing VCOMP to a triangle wave (duty = VCOMP/VPP RAMP). The low-pass filter formed by L and CO convert the duty cycle to a DC output voltage (Vo = VDCIN*duty). In ISL6257, the triangle wave amplitude is proportional to VDCIN. Making the ramp amplitude proportional to DCIN makes the gain from VCOMP to the PHASE output a constant 11 and is independent of DCIN.
VDD RAMP GEN VRAMP = VDD/11 L VCOMP + DRIVERS
CO RESR
L VCOMP 11 CO RESR
FIGURE 21. FOR SMALL SIGNAL AC ANALYSIS, THE PWM AND POWER STAGE CAN BE MODELED AS A SIMPLE GAIN OF 11.
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Output LC Filter Transfer Functions The gain from the phase node to the system output and battery depend entirely on external components. Transfer function ALC(s) is shown in Equation 21 and Equation 22:
s 1 - ------------- ESR A LC = --------------------------------------------------------- s2 s ---------- + ------------------------ + 1 DP ( DP Q ) 1 ESR = ----------------------------( R ESR C o ) 1 DP = ---------------------( L Co )
voltage buffer output equals the voltage on VCOMP. The voltage control loop is shown in Figure 23.
RAMP GEN VRAMP = VDD/11 DRIVERS VDD L PHASE ISYSTEM
(EQ. 21)
+
CO RESR
L Q = R o -----Co (EQ. 22)
FB VCOMP R2 C2 R1 C1
CSON
RS2
RBAT R3
gm1
NO BATTERY GAIN (dB) RBATTERY = 100m RBATTERY = 50m
+
VREF =2.1V
R4
FOR SMALL SIGNAL AC ANALYSIS, VOLTAGE SOURCES ARE SHORT CIRCUITS AND CURRENT SOURCES ARE OPEN CIRCUITS. L
PHASE (DEGREES)
11 PHASE CO RESR FB VCOMP R2
FREQUENCY
RS2
CSON R1 C1 RBAT R3 R4
C2
gm1
-
FIGURE 22. FREQUENCY RESPONSE OF THE LC OUTPUT FILTER
+
The load resistance RO is a combination of MOSFET rDS(ON), inductor DCR and the internal resistance of the battery (normally between 50m and 200m) in parallel with the system. The system load may be modeled as a current sink in parallel with a resistance. For AC analysis of the voltage control loop this may be treated as a very high resistance or an open circuit. The worst case for voltage mode control is when the battery is absent. This results in the highest Q of the LC filter and the lowest phase margin. Voltage Control Loop The voltage error amplifier controls the output when the battery is not drawing current and the input current is below the limit. Under these conditions VCOMP controls the charger's output because the 2 current error amplifiers (gm2 and gm3) output their maximum current and charge the capacitor on ICOMP to its maximum voltage (limited to 1.2V above VCOMP). With high voltage on ICOMP, the minimum
FIGURE 23. VOLTAGE LOOP COMPENSATOR
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The compensation network consists of the voltage error amplifier gm1 and the compensation network R1, C1, R2 and C2. R3 and R4 are internal divider resisters that set the DC output voltage. For a 3 cell battery, R3 = 320k and R4 = 64k. The equations below relate the compensation network's poles, zeros and gain to the components in Figure 20. Figure 24 shows an asymptotic Bode plot of the DC/DC converter's gain vs. frequency. It is strongly recommended that FZ1 is approximately 1/4*FDP and FZ2 is approximately 1/2*FDP.
60 50 40 30
GAIN (dB)
Charge Current Control Loop When the battery voltage is less than the fully charged voltage, the voltage error amplifier goes to it's maximum output (limited to 1.2V above ICOMP) and the ICOMP voltage controls the loop through the minimum voltage buffer. Figure 25 shows the charge current control loop.
L 11 PHASE CO RESR
Loop Modulator Compensator
S
ICOMP CICOMP
+
0.25
CSOP +
20 CA2
RF2 CF2 RS2
F DP
-
CSON
20 10 0 -10 -20 -30 -40
0.01 0.1 1
gm2
+
RBAT CHLIM +
F P1
-
F Z1 F Z2 FZESR
10 100 1000
FIGURE 25. CHARGE CURRENT LIMIT LOOP
FREQUENCY (kHz)
The compensation capacitor (CICOMP) gives the error amplifier (gm2) a pole at a very low frequency (<<1Hz) and a a zero at FZ1. FZ1 is created by the 0.25*CA2 output added to ICOMP. The loop response has another zero due to the output capacitor's esr. A filter should be added between RS2 and CSOP and CSON to reduce switching noise. The filter roll off frequency should be between the cross over frequency and the switching frequency (~100kHz). RF2 should be small (<10) to minimize offsets due to leakage current into CSOP.
1 F DP = -----------------------------( 2 L C o ) 1 F ZESR = ---------------------------------------( 2 C o R ESR ) 4 gm2 F Z1 = ------------------------------------( 2 C ICOMP ) 1 F FILTER = ---------------------------------------( 2 C F2 R F2 ) (EQ. 27)
FIGURE 24. ASYMPTOTIC BODE PLOT OF THE VOLTAGE CONTROL LOOP GAIN
Compensation Break Frequency Equations
1 F Z1 = -------------------------------------------------( 2 C 1 ( R 1 + R 3 ) ) 1 F Z2 = --------------------------------------------------------- 1 2 C 2 R 2 - ---------- gm1 1 F DP = -----------------------------( 2 L C o ) 1 F ESR = ---------------------------------------( 2 C o R ESR ) TABLE 3. CELLS 2 3 4 R3 288k 320k 336k (EQ. 23)
1 ---------- = 4.17k gm1 (EQ. 24) 1 F P1 = --------------------------------( 2 R 1 C 1 )
(EQ. 28)
(EQ. 25) (EQ. 26)
gm2 = 50A V
(EQ. 29)
(EQ. 30)
19
FN9288.2 January 17, 2007
ISL6257
60
DCIN
F DP
Compensator Modulator Loop
40
RS1 11 RF1 PHASE
L CO RESR
20 GAIN (dB)
CF1
0
F Z1
-20
F
S
FILTER
+
0.25
CSOP +
20 CA2
RF2 CF2 RS2
-
CSON
CSIN
- 20
+
CA1
-40
CSIP
RBAT
F
-60 0.01 0.1 1
ZESR
gm3
-
10
100
1000
ICOMP CICOMP
+ ACLIM +
FREQUENCY (kHz)
-
FIGURE 26. CHARGE CURRENT LOOP BODE PLOTS
CICOMP should be chosen using Equation 31 to set FZ1 = FDP/10. The crossover frequency will be approximately 2.5 * FDP. The phase margin will be between +10C and +40C depending on FZESR.
4 gm2 C ICOMP = ------------------------------2 F DP 10 (EQ. 31)
FIGURE 27. ADAPTER CURRENT LIMIT LOOP
The loop response equations, bode plots and the selection of CICOMP are the same as the charge current control loop with loop gain reduced by the duty cycle. In other words, if the duty cycle D = 50%, the loop gain will be 6dB lower than the loop gain in Figure 26. This gives lower crossover frequency and higher phase margin in this mode.
Adapter Current Limit Control Loop If the combined battery charge current and system load current draws current that equals the adapter current limit set by the ACLIM pin, ISL6257 will reduce the current to the battery and/or reduce the output voltage to hold the adapter current at the limit. Figure 17 shows the effect on output voltage as the load current is swept up beyond the adapter current limit. Above the adapter current limit the minimum current buffer equals the output of gm3 and ICOMP controls the charger output. Figure 27 shows the resulting adapter current control system. A filter should be added between RS1 and CSIP and CSIN to reduce switching noise. The filter roll off frequency should be between the cross over frequency and the switching frequency (~100kHz).
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. As an example, layer arrangement on a 4-layer board is shown below: 1. Top Layer: signal lines, or half board for signal lines and the other half board for power lines 2. Signal Ground 3. Power Layers: Power Ground 4. Bottom Layer: Power MOSFET, Inductors and other Power traces Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will stay on the signal layer, which is isolated by the signal ground to the power signal traces.
20
FN9288.2 January 17, 2007
ISL6257
Component Placement
The power MOSFET should be close to the IC so that the gate drive signal, the LGATE, UGATE, PHASE, and BOOT, traces can be short. Place the components in such a way that the area under the IC has less noise traces with high dV/dt and di/dt, such as gate signals and phase node signals.
BOOT Pin
This pin's di/dt is as high as the UGATE; therefore, this trace should be as short as possible.
CSIP, CSIN Pins
The input current sense resistor connects to the CSIP and CSIN pins through a low pass filter. The traces should be away and guarded/shielded from the high dV/dt and di/dt nodes like Phase, Boot.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will shield other noise couplings through the IC, should be used as signal ground beneath the IC. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the IC is not recommended.
CSOP, CSON Pins
The charging current sense resistor connects to the CSOP and the CSON pins through a low pass filter. The traces should be away and guarded/shielded from the high dV/dt and di/dt nodes like PHASE, BOOT. In general, the current sense resistor should be close to the IC.
GND and VDD Pin
At least one high quality ceramic decoupling cap should be used to cross these two pins. The decoupling cap can be put close to the IC.
EN Pin
This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the buck converter. The signal going through this trace has both high dV/dt and high di/dt, and the peak charging and discharging current is very high. These two traces should be short, wide, and away from other traces. There should be no other traces in parallel with these traces on any layer.
DCIN Pin
This pin connects to AC adapter output voltage, and should be less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to minimize ringing. It would be best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application.
PGND Pin
PGND pin should be laid out to the negative side of the relevant output cap with separate traces.The negative side of the output capacitor must be close to the source node of the bottom MOSFET. This trace is the return path of LGATE.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source terminal of the bottom switching MOSFET PGND should connect to the power ground. The other components should connect to signal ground. Signal and power ground are tied together at one point.
PHASE Pin
This trace should be short, and positioned away from other weak signal traces. This node has a very high dV/dt with a voltage swing from the input voltage to ground. No trace should be in parallel with it. This trace is also the return path for UGATE. Connect this pin to the high-side MOSFET source.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely connected to the drain of the high-side MOSFET, and the source of the low-side MOSFET. This capacitor reduces the noise and the power loss of the MOSFET.
UGATE Pin
This pin has a square shape waveform with high dV/dt. It provides the gate drive current to charge and discharge the top MOSFET with high di/dt. This trace should be wide, short, and away from other traces similar to the LGATE.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN9288.2 January 17, 2007
ISL6257 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 0 4X C TOP VIEW A2 A / / 0.10 C 0.08 C SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 9 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.50 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.25 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.60 28 7 7 0.60 12 0.75 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 2 3 3 9 9 Rev. 1 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
SEATING PLANE
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 e 10 L
L1 e CC
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
22
FN9288.2 January 17, 2007

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